Digital circuitry is being implemented in increasing numbers of systems which have traditionally been realized with analog circuits for the reasons that (a) digital circuitry is inherently more stable parametrically and (b) advances in digital integrated circuitry are making them cost competitive. Examples of systems that are currently being implemented with digital processing are television systems such as receivers, video cassette recorders, etc., and sound systems such as compact disc players, digital audio tape players, etc. In the above mentioned systems it is frequently necessary to generate clock signals which are phase locked to a component of the signal to be processed. Digital television receivers, for example, are often designed to operate synchronously with the chrominance subcarrier. To facilitate such synchronism the television signal includes a burst of oscillations at the subcarrier frequency, which oscillations are of appropriate phase and occur in a nonactive portion of each video line interval.
A clock signal can be generated which is phase locked to the subcarrier frequency by (a) sampling the burst component to produce substantially quadrature phase related samples of the burst signal; (b) accumulating the respective quadrature samples; and (c) generating a signal for controlling a VCO which develops clock signals that determine the sampling intervals. One such system is disclosed in U.S. Pat. No. 4,491,862 entitled "Color Television Receiver With at Least One Digital Integrated Circuit For Processing the Composite Color Signal," issued to Peter Flamm. The Flamm system includes an analog to digital converter (ADC) which is conditioned by a VCO to sample the video signal at four times the subcarrier frequency. Alternate ones of the samples are quadrature related once the system is phase locked. The samples produced by the ADC are separated into two components corresponding to alternate samples, i.e. an R-Y signal and a B-Y signal both of which are modulated at the subcarrier frequency. Alternate ones of each of the components (the R-Y samples of positive sampling phase and the B-Y samples of positive sampling phase) are accumulated in separate accumulators that are conditioned to operate only on samples taken during burst intervals. The sign (polarity) bits of the accumulated R-Y and B-Y samples are coupled to a switching circuit. The R-Y accumulated samples are applied to a value limiter circuit, and the limited samples coupled to the switching circuit. The sign bits of the accumulated samples indicate whether the phase of the clock signal generated by the VCO is greater or less than + or -90.degree. relative to the phase of the B-Y component. Depending upon the states of the sign bits the switching circuit provides output values equal to a predetermined positive value, a predetermined negative value or the accumulated R-Y values provided by the limiter circuit. The output of the switching circuit is low pass filtered, converted to an analog signal, and applied to the control input of the VCO to form a closed loop phase locked clock generator.
There are at least two shortcomings of the Flamm circuitry. Firstly the phase detection is a function of signal amplitude. The detection accuracy diminishes with smaller signal amplitude. Secondly, since phase detection is amplitude sensitive, the system is subject to phase error if the burst signal contains a DC component. DC components are frequently introduced due to parametric shifts in the ADC or improper biasing of the ADC.
It is an object of the invention to provide a sampled data phase locking system without the foregoing shortcomings.